* Copyright (C) 2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/*==========================================================================*/
+/*!
+ * @file
*
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
+ * Header file used to configure SoC pin list.
*/
+/*==========================================================================*/
+
+/* DO NOT EDIT - This file auto generated by bin/pins_h.pl */
#ifndef _SC_PINS_H
#define _SC_PINS_H
-#define SC_P_ALL UINT16_MAX
+/* Includes */
-/*
+/* Defines */
+
+#define SC_P_ALL UINT16_MAX //!< All pins
+
+/*!
* @name Pin Definitions
*/
-#define SC_P_PCIE_CTRL0_CLKREQ_B 0
-#define SC_P_PCIE_CTRL0_WAKE_B 1
-#define SC_P_PCIE_CTRL0_PERST_B 2
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3
-#define SC_P_USB_SS3_TC0 4
-#define SC_P_USB_SS3_TC1 5
-#define SC_P_USB_SS3_TC2 6
-#define SC_P_USB_SS3_TC3 7
-#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8
-#define SC_P_EMMC0_CLK 9
-#define SC_P_EMMC0_CMD 10
-#define SC_P_EMMC0_DATA0 11
-#define SC_P_EMMC0_DATA1 12
-#define SC_P_EMMC0_DATA2 13
-#define SC_P_EMMC0_DATA3 14
-#define SC_P_EMMC0_DATA4 15
-#define SC_P_EMMC0_DATA5 16
-#define SC_P_EMMC0_DATA6 17
-#define SC_P_EMMC0_DATA7 18
-#define SC_P_EMMC0_STROBE 19
-#define SC_P_EMMC0_RESET_B 20
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 21
-#define SC_P_USDHC1_RESET_B 22
-#define SC_P_USDHC1_VSELECT 23
-#define SC_P_USDHC1_WP 24
-#define SC_P_USDHC1_CD_B 25
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 26
-#define SC_P_USDHC1_CLK 27
-#define SC_P_USDHC1_CMD 28
-#define SC_P_USDHC1_DATA0 29
-#define SC_P_USDHC1_DATA1 30
-#define SC_P_USDHC1_DATA2 31
-#define SC_P_USDHC1_DATA3 32
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 33
-#define SC_P_ENET0_RGMII_TXC 34
-#define SC_P_ENET0_RGMII_TX_CTL 35
-#define SC_P_ENET0_RGMII_TXD0 36
-#define SC_P_ENET0_RGMII_TXD1 37
-#define SC_P_ENET0_RGMII_TXD2 38
-#define SC_P_ENET0_RGMII_TXD3 39
-#define SC_P_ENET0_RGMII_RXC 40
-#define SC_P_ENET0_RGMII_RX_CTL 41
-#define SC_P_ENET0_RGMII_RXD0 42
-#define SC_P_ENET0_RGMII_RXD1 43
-#define SC_P_ENET0_RGMII_RXD2 44
-#define SC_P_ENET0_RGMII_RXD3 45
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 46
-#define SC_P_ENET0_REFCLK_125M_25M 47
-#define SC_P_ENET0_MDIO 48
-#define SC_P_ENET0_MDC 49
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 50
-#define SC_P_FLEXCAN0_RX 51
-#define SC_P_FLEXCAN0_TX 52
-#define SC_P_FLEXCAN1_RX 53
-#define SC_P_FLEXCAN1_TX 54
-#define SC_P_UART0_RX 55
-#define SC_P_UART0_TX 56
-#define SC_P_UART0_RTS_B 57
-#define SC_P_UART0_CTS_B 58
-#define SC_P_UART1_TX 59
-#define SC_P_UART1_RX 60
-#define SC_P_UART1_RTS_B 61
-#define SC_P_UART1_CTS_B 62
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 63
-#define SC_P_SPI0_SCK 64
-#define SC_P_SPI0_SDO 65
-#define SC_P_SPI0_SDI 66
-#define SC_P_SPI0_CS0 67
-#define SC_P_SPI0_CS1 68
-#define SC_P_SPI2_SCK 69
-#define SC_P_SPI2_SDO 70
-#define SC_P_SPI2_SDI 71
-#define SC_P_SPI2_CS0 72
-#define SC_P_SPI2_CS1 73
-#define SC_P_SAI1_RXC 74
-#define SC_P_SAI1_RXD 75
-#define SC_P_SAI1_RXFS 76
-#define SC_P_SAI1_TXC 77
-#define SC_P_SAI1_TXD 78
-#define SC_P_SAI1_TXFS 79
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 80
-#define SC_P_ESAI0_FSR 81
-#define SC_P_ESAI0_FST 82
-#define SC_P_ESAI0_SCKR 83
-#define SC_P_ESAI0_SCKT 84
-#define SC_P_ESAI0_TX0 85
-#define SC_P_ESAI0_TX1 86
-#define SC_P_ESAI0_TX2_RX3 87
-#define SC_P_ESAI0_TX3_RX2 88
-#define SC_P_ESAI0_TX4_RX1 89
-#define SC_P_ESAI0_TX5_RX0 90
-#define SC_P_SPDIF0_RX 91
-#define SC_P_SPDIF0_TX 92
-#define SC_P_SPDIF0_EXT_CLK 93
-#define SC_P_SPI3_SCK 94
-#define SC_P_SPI3_SDO 95
-#define SC_P_SPI3_SDI 96
-#define SC_P_SPI3_CS0 97
-#define SC_P_SPI3_CS1 98
-#define SC_P_MCLK_IN0 99
-#define SC_P_MCLK_OUT0 100
-#define SC_P_FTM0 101
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 102
-#define SC_P_ADC_IN1 103
-#define SC_P_ADC_IN0 104
-#define SC_P_ADC_IN3 105
-#define SC_P_ADC_IN2 106
-#define SC_P_CSI_D00 107
-#define SC_P_CSI_D01 108
-#define SC_P_CSI_D02 109
-#define SC_P_CSI_D03 110
-#define SC_P_CSI_D04 111
-#define SC_P_CSI_D05 112
-#define SC_P_CSI_D06 113
-#define SC_P_CSI_D07 114
-#define SC_P_CSI_HSYNC 115
-#define SC_P_CSI_VSYNC 116
-#define SC_P_CSI_PCLK 117
-#define SC_P_CSI_MCLK 118
-#define SC_P_CSI_EN 119
-#define SC_P_CSI_RESET 120
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 121
-#define SC_P_PMIC_I2C_SCL 122
-#define SC_P_PMIC_I2C_SDA 123
-#define SC_P_PMIC_INT_B 124
-#define SC_P_SCU_GPIO0_00 125
-#define SC_P_SCU_GPIO0_01 126
-#define SC_P_SCU_BOOT_MODE0 127
-#define SC_P_SCU_BOOT_MODE1 128
-#define SC_P_SCU_BOOT_MODE2 129
-#define SC_P_SCU_BOOT_MODE3 130
-#define SC_P_MIPI_DSI0_I2C0_SCL 131
-#define SC_P_MIPI_DSI0_I2C0_SDA 132
-#define SC_P_MIPI_DSI0_GPIO0_00 133
-#define SC_P_MIPI_DSI0_GPIO0_01 134
-#define SC_P_MIPI_DSI1_I2C0_SCL 135
-#define SC_P_MIPI_DSI1_I2C0_SDA 136
-#define SC_P_MIPI_DSI1_GPIO0_00 137
-#define SC_P_MIPI_DSI1_GPIO0_01 138
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 139
-#define SC_P_MIPI_CSI0_MCLK_OUT 140
-#define SC_P_MIPI_CSI0_I2C0_SCL 141
-#define SC_P_MIPI_CSI0_I2C0_SDA 142
-#define SC_P_MIPI_CSI0_GPIO0_00 143
-#define SC_P_MIPI_CSI0_GPIO0_01 144
-#define SC_P_QSPI0A_DATA0 145
-#define SC_P_QSPI0A_DATA1 146
-#define SC_P_QSPI0A_DATA2 147
-#define SC_P_QSPI0A_DATA3 148
-#define SC_P_QSPI0A_DQS 149
-#define SC_P_QSPI0A_SS0_B 150
-#define SC_P_QSPI0A_SS1_B 151
-#define SC_P_QSPI0A_SCLK 152
-#define SC_P_QSPI0B_SCLK 153
-#define SC_P_QSPI0B_DATA0 154
-#define SC_P_QSPI0B_DATA1 155
-#define SC_P_QSPI0B_DATA2 156
-#define SC_P_QSPI0B_DATA3 157
-#define SC_P_QSPI0B_DQS 158
-#define SC_P_QSPI0B_SS0_B 159
-#define SC_P_QSPI0B_SS1_B 160
-#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 161
-#define SC_P_XTALI 162
-#define SC_P_XTALO 163
-#define SC_P_ANA_TEST_OUT_P 164
-#define SC_P_ANA_TEST_OUT_N 165
-#define SC_P_RTC_XTALI 166
-#define SC_P_RTC_XTALO 167
-#define SC_P_PMIC_ON_REQ 168
-#define SC_P_ON_OFF_BUTTON 169
+/*@{*/
+#define SC_P_PCIE_CTRL0_CLKREQ_B 0 //!< HSIO.PCIE0.CLKREQ_B, LSIO.GPIO0.IO04
+#define SC_P_PCIE_CTRL0_WAKE_B 1 //!< HSIO.PCIE0.WAKE_B, LSIO.GPIO0.IO05
+#define SC_P_PCIE_CTRL0_PERST_B 2 //!< HSIO.PCIE0.PERST_B, LSIO.GPIO0.IO06
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3 //!<
+#define SC_P_USB_SS3_TC0 4 //!< ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO0.IO00
+#define SC_P_USB_SS3_TC1 5 //!< ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO0.IO01
+#define SC_P_USB_SS3_TC2 6 //!< ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO0.IO02
+#define SC_P_USB_SS3_TC3 7 //!< ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO0.IO03
+#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8 //!<
+#define SC_P_EMMC0_CLK 9 //!< CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.KPP0.COL0, LSIO.GPIO0.IO17
+#define SC_P_EMMC0_CMD 10 //!< CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.KPP0.COL1, LSIO.GPIO0.IO18
+#define SC_P_EMMC0_DATA0 11 //!< CONN.EMMC0.DATA0, CONN.NAND.DATA00, LSIO.KPP0.COL2, LSIO.GPIO0.IO19
+#define SC_P_EMMC0_DATA1 12 //!< CONN.EMMC0.DATA1, CONN.NAND.DATA01, LSIO.KPP0.COL3, LSIO.GPIO0.IO20
+#define SC_P_EMMC0_DATA2 13 //!< CONN.EMMC0.DATA2, CONN.NAND.DATA02, LSIO.KPP0.COL4, LSIO.GPIO0.IO21
+#define SC_P_EMMC0_DATA3 14 //!< CONN.EMMC0.DATA3, CONN.NAND.DATA03, LSIO.KPP0.COL5, LSIO.GPIO0.IO22
+#define SC_P_EMMC0_DATA4 15 //!< CONN.EMMC0.DATA4, CONN.NAND.DATA04, LSIO.KPP0.ROW0, CONN.EMMC0.WP
+#define SC_P_EMMC0_DATA5 16 //!< CONN.EMMC0.DATA5, CONN.NAND.DATA05, LSIO.KPP0.ROW1, CONN.EMMC0.VSELECT
+#define SC_P_EMMC0_DATA6 17 //!< CONN.EMMC0.DATA6, CONN.NAND.DATA06, LSIO.KPP0.ROW2, CONN.MLB.CLK
+#define SC_P_EMMC0_DATA7 18 //!< CONN.EMMC0.DATA7, CONN.NAND.DATA07, LSIO.KPP0.ROW3, CONN.MLB.SIG
+#define SC_P_EMMC0_STROBE 19 //!< CONN.EMMC0.STROBE, CONN.NAND.CLE, LSIO.KPP0.ROW4, CONN.MLB.DATA
+#define SC_P_EMMC0_RESET_B 20 //!< CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.KPP0.ROW5, LSIO.GPIO0.IO28
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX 21 //!<
+#define SC_P_USDHC1_RESET_B 22 //!< CONN.USDHC1.RESET_B, CONN.NAND.RE_N, CONN.MLB.SIG, LSIO.GPIO0.IO07
+#define SC_P_USDHC1_VSELECT 23 //!< CONN.USDHC1.VSELECT, CONN.NAND.RE_P, CONN.MLB.CLK, LSIO.GPIO0.IO08
+#define SC_P_USDHC1_WP 24 //!< CONN.USDHC1.WP, CONN.NAND.DQS_N, LSIO.GPIO0.IO09
+#define SC_P_USDHC1_CD_B 25 //!< CONN.USDHC1.CD_B, CONN.NAND.DQS_P, CONN.MLB.DATA, LSIO.GPIO0.IO10
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 26 //!<
+#define SC_P_USDHC1_CLK 27 //!< CONN.USDHC1.CLK, ADMA.MQS.R, LSIO.GPIO0.IO11
+#define SC_P_USDHC1_CMD 28 //!< CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.L, LSIO.GPIO0.IO12
+#define SC_P_USDHC1_DATA0 29 //!< CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.UART4.RX, LSIO.GPIO0.IO13
+#define SC_P_USDHC1_DATA1 30 //!< CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART4.TX, LSIO.GPIO0.IO14
+#define SC_P_USDHC1_DATA2 31 //!< CONN.USDHC1.DATA2, CONN.NAND.WE_B, ADMA.UART4.CTS_B, LSIO.GPIO0.IO15
+#define SC_P_USDHC1_DATA3 32 //!< CONN.USDHC1.DATA3, CONN.NAND.ALE, ADMA.UART4.RTS_B, LSIO.GPIO0.IO16
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_VSEL3 33 //!<
+#define SC_P_ENET0_RGMII_TXC 34 //!< CONN.ENET0.RGMII_TXC, CONN.ENET0.RCLK50M_OUT, CONN.ENET0.RCLK50M_IN, CONN.NAND.CE1_B
+#define SC_P_ENET0_RGMII_TX_CTL 35 //!< CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B
+#define SC_P_ENET0_RGMII_TXD0 36 //!< CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT
+#define SC_P_ENET0_RGMII_TXD1 37 //!< CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP
+#define SC_P_ENET0_RGMII_TXD2 38 //!< CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, LSIO.GPIO1.IO05
+#define SC_P_ENET0_RGMII_TXD3 39 //!< CONN.ENET0.RGMII_TXD3, CONN.MLB.SIG, CONN.NAND.RE_B, CONN.USDHC1.CD_B
+#define SC_P_ENET0_RGMII_RXC 40 //!< CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK
+#define SC_P_ENET0_RGMII_RX_CTL 41 //!< CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD
+#define SC_P_ENET0_RGMII_RXD0 42 //!< CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0
+#define SC_P_ENET0_RGMII_RXD1 43 //!< CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1
+#define SC_P_ENET0_RGMII_RXD2 44 //!< CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2
+#define SC_P_ENET0_RGMII_RXD3 45 //!< CONN.ENET0.RGMII_RXD3, CONN.NAND.ALE, CONN.USDHC1.DATA3
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB 46 //!<
+#define SC_P_ENET0_REFCLK_125M_25M 47 //!< CONN.ENET0.REFCLK_125M_25M, CONN.ENET0.PPS, CONN.ENET1.PPS, LSIO.GPIO1.IO00
+#define SC_P_ENET0_MDIO 48 //!< CONN.ENET0.MDIO, ADMA.I2C4.SDA, CONN.ENET1.MDIO, LSIO.GPIO0.IO29
+#define SC_P_ENET0_MDC 49 //!< CONN.ENET0.MDC, ADMA.I2C4.SCL, CONN.ENET1.MDC, LSIO.GPIO0.IO30
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOCT 50 //!<
+#define SC_P_FLEXCAN0_RX 51 //!< ADMA.FLEXCAN0.RX, M40.GPIO0.IO02, LSIO.GPIO3.IO10
+#define SC_P_FLEXCAN0_TX 52 //!< ADMA.FLEXCAN0.TX, M40.GPIO0.IO03, LSIO.GPIO3.IO11
+#define SC_P_FLEXCAN1_RX 53 //!< ADMA.FLEXCAN1.RX, M40.GPIO0.IO00, ADMA.UART3.RX, LSIO.GPIO3.IO12
+#define SC_P_FLEXCAN1_TX 54 //!< ADMA.FLEXCAN1.TX, M40.GPIO0.IO01, ADMA.UART3.TX, LSIO.GPIO3.IO13
+#define SC_P_UART0_RX 55 //!< ADMA.UART0.RX, M40.UART0.RX, M40.I2C0.SCL, LSIO.GPIO3.IO14
+#define SC_P_UART0_TX 56 //!< ADMA.UART0.TX, M40.UART0.TX, M40.I2C0.SDA, LSIO.GPIO3.IO15
+#define SC_P_UART0_RTS_B 57 //!< ADMA.UART0.RTS_B, LSIO.PWM0.OUT, ADMA.UART2.RX, LSIO.GPIO3.IO16
+#define SC_P_UART0_CTS_B 58 //!< ADMA.UART0.CTS_B, LSIO.PWM1.OUT, ADMA.UART2.TX, LSIO.GPIO3.IO17
+#define SC_P_UART1_TX 59 //!< ADMA.UART1.TX, LSIO.GPT0.CLK, LSIO.PWM2.OUT, LSIO.GPIO3.IO18
+#define SC_P_UART1_RX 60 //!< ADMA.UART1.RX, LSIO.GPT0.CAPTURE, LSIO.PWM3.OUT, LSIO.GPIO3.IO19
+#define SC_P_UART1_RTS_B 61 //!< ADMA.UART1.RTS_B, LSIO.GPT0.COMPARE, ADMA.UART1.CTS_B, LSIO.GPIO3.IO20
+#define SC_P_UART1_CTS_B 62 //!< ADMA.UART1.CTS_B, ADMA.UART1.RTS_B, LSIO.GPIO3.IO21
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 63 //!<
+#define SC_P_SPI0_SCK 64 //!< ADMA.SPI0.SCK, ADMA.SAI0.RXC, LSIO.GPIO2.IO21
+#define SC_P_SPI0_SDO 65 //!< ADMA.SPI0.SDO, ADMA.SAI0.TXD, LSIO.GPIO2.IO22
+#define SC_P_SPI0_SDI 66 //!< ADMA.SPI0.SDI, ADMA.SAI0.RXD, LSIO.GPIO2.IO23
+#define SC_P_SPI0_CS0 67 //!< ADMA.SPI0.CS0, ADMA.SAI0.RXFS, LSIO.GPIO2.IO24
+#define SC_P_SPI0_CS1 68 //!< ADMA.SPI0.CS1, ADMA.SAI0.TXC, ADMA.SAI1.TXD, LSIO.GPIO2.IO25
+#define SC_P_SPI2_SCK 69 //!< ADMA.SPI2.SCK, LSIO.GPIO2.IO26
+#define SC_P_SPI2_SDO 70 //!< ADMA.SPI2.SDO, LSIO.GPIO2.IO27
+#define SC_P_SPI2_SDI 71 //!< ADMA.SPI2.SDI, LSIO.GPIO2.IO28
+#define SC_P_SPI2_CS0 72 //!< ADMA.SPI2.CS0, LSIO.GPIO2.IO29
+#define SC_P_SPI2_CS1 73 //!< ADMA.SAI0.TXFS, ADMA.SPI2.CS1, ADMA.SPI1.SCK, LSIO.GPIO2.IO30
+#define SC_P_SAI1_RXC 74 //!< ADMA.SAI0.TXD, ADMA.SAI1.RXC, ADMA.SPI1.SDO, LSIO.GPIO3.IO01
+#define SC_P_SAI1_RXD 75 //!< ADMA.SAI0.TXC, ADMA.SAI1.TXD, ADMA.SPI1.SDI, LSIO.GPIO3.IO01
+#define SC_P_SAI1_RXFS 76 //!< ADMA.SAI0.RXD, ADMA.SAI1.RXFS, ADMA.SPI1.CS0, LSIO.GPIO3.IO02
+#define SC_P_SAI1_TXC 77 //!< ADMA.SAI1.RXC, ADMA.SAI1.TXC, ADMA.FLEXCAN2.RX, LSIO.GPIO3.IO03
+#define SC_P_SAI1_TXD 78 //!< ADMA.SAI1.RXD, ADMA.SAI0.TXFS, ADMA.SPI1.CS1, LSIO.GPIO3.IO04
+#define SC_P_SAI1_TXFS 79 //!< ADMA.SAI1.RXFS, ADMA.SAI1.TXFS, ADMA.FLEXCAN2.TX, LSIO.GPIO3.IO05
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHT 80 //!<
+#define SC_P_ESAI0_FSR 81 //!< ADMA.ESAI0.FSR, CONN.ENET1.RCLK50M_OUT, CONN.ENET1.RGMII_TXC
+#define SC_P_ESAI0_FST 82 //!< ADMA.ESAI0.FST, CONN.ENET1.RGMII_TX_CTL
+#define SC_P_ESAI0_SCKR 83 //!< ADMA.ESAI0.SCKR, CONN.ENET1.RGMII_TXD0
+#define SC_P_ESAI0_SCKT 84 //!< ADMA.ESAI0.SCKT, CONN.ENET1.RGMII_TXD1
+#define SC_P_ESAI0_TX0 85 //!< ADMA.ESAI0.TX0, CONN.MLB.CLK, CONN.ENET1.RGMII_TXD2
+#define SC_P_ESAI0_TX1 86 //!< ADMA.ESAI0.TX1, CONN.MLB.SIG, CONN.ENET1.RGMII_TXD3
+#define SC_P_ESAI0_TX2_RX3 87 //!< ADMA.ESAI0.TX2_RX3, CONN.MLB.DATA, CONN.ENET1.RGMII_RXC
+#define SC_P_ESAI0_TX3_RX2 88 //!< ADMA.ESAI0.TX3_RX2, CONN.ENET1.RGMII_RX_CTL
+#define SC_P_ESAI0_TX4_RX1 89 //!< ADMA.ESAI0.TX4_RX1, ADMA.MQS.R, CONN.ENET1.RGMII_RXD0
+#define SC_P_ESAI0_TX5_RX0 90 //!< ADMA.ESAI0.TX5_RX0, ADMA.MQS.L, CONN.ENET1.RGMII_RXD1
+#define SC_P_SPDIF0_RX 91 //!< ADMA.SPDIF0.RX, CONN.ENET1.RMII_RX_ER, CONN.ENET1.RGMII_RXD2
+#define SC_P_SPDIF0_TX 92 //!< ADMA.SPDIF0.TX, CONN.ENET1.RCLK50M_IN, CONN.ENET1.RGMII_RXD3
+#define SC_P_SPDIF0_EXT_CLK 93 //!< ADMA.SPDIF0.EXT_CLK, CONN.ENET1.REFCLK_125M_25M
+#define SC_P_SPI3_SCK 94 //!< ADMA.SPI3.SCK, LSIO.GPIO2.IO13
+#define SC_P_SPI3_SDO 95 //!< ADMA.SPI3.SDO, LSIO.GPIO2.IO14
+#define SC_P_SPI3_SDI 96 //!< ADMA.SPI3.SDI, ADMA.FTM.CH1, LSIO.GPIO2.IO15
+#define SC_P_SPI3_CS0 97 //!< ADMA.SPI3.CS0, ADMA.FTM.CH2, LSIO.GPIO2.IO16
+#define SC_P_SPI3_CS1 98 //!< ADMA.SPI3.CS1, ADMA.DMA0.REQ_IN0, LSIO.GPIO2.IO17
+#define SC_P_MCLK_IN0 99 //!< ADMA.ACM.MCLK_IN0, ADMA.ESAI0.RX_HF_CLK, LSIO.GPIO2.IO18
+#define SC_P_MCLK_OUT0 100 //!< ADMA.ACM.MCLK_OUT0, ADMA.ESAI0.TX_HF_CLK, LSIO.GPIO2.IO19
+#define SC_P_FTM0 101 //!< ADMA.FTM.CH0, LSIO.GPIO2.IO20
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB 102 //!<
+#define SC_P_ADC_IN1 103 //!< ADMA.ADC.IN1, M40.I2C0.SDA, M40.UART0.TX, LSIO.GPIO3.IO07
+#define SC_P_ADC_IN0 104 //!< ADMA.ADC.IN0, M40.I2C0.SCL, M40.UART0.RX, LSIO.GPIO3.IO06
+#define SC_P_ADC_IN3 105 //!< ADMA.ADC.IN3, M40.GPIO0.IO01, M40.TPM0.CH1, LSIO.GPIO3.IO09
+#define SC_P_ADC_IN2 106 //!< ADMA.ADC.IN2, M40.GPIO0.IO00, M40.TPM0.CH0, LSIO.GPIO3.IO08
+#define SC_P_CSI_D00 107 //!< CI_PI.D00, SNVS.TAMPER_OUT0
+#define SC_P_CSI_D01 108 //!< CI_PI.D01, SNVS.TAMPER_OUT1
+#define SC_P_CSI_D02 109 //!< CI_PI.D02, SNVS.TAMPER_OUT2
+#define SC_P_CSI_D03 110 //!< CI_PI.D03, SNVS.TAMPER_OUT3
+#define SC_P_CSI_D04 111 //!< CI_PI.D04, SNVS.TAMPER_OUT4
+#define SC_P_CSI_D05 112 //!< CI_PI.D05, SNVS.TAMPER_IN0
+#define SC_P_CSI_D06 113 //!< CI_PI.D06, SNVS.TAMPER_IN1
+#define SC_P_CSI_D07 114 //!< CI_PI.D07, SNVS.TAMPER_IN2
+#define SC_P_CSI_HSYNC 115 //!< CI_PI.HSYNC, CI_PI.D08, SNVS.TAMPER_IN3
+#define SC_P_CSI_VSYNC 116 //!< CI_PI.VSYNC, CI_PI.D09, SNVS.TAMPER_IN4
+#define SC_P_CSI_PCLK 117 //!< CI_PI.PCLK, LSIO.GPT1.CLK
+#define SC_P_CSI_MCLK 118 //!< CI_PI.MCLK
+#define SC_P_CSI_EN 119 //!< CI_PI.EN, LSIO.GPT1.CAPTURE, CI_PI.D08
+#define SC_P_CSI_RESET 120 //!< CI_PI.RESET, LSIO.GPT1.COMPARE, CI_PI.D09
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 121 //!<
+#define SC_P_PMIC_I2C_SCL 122 //!< SCU.PMIC_I2C.SCL
+#define SC_P_PMIC_I2C_SDA 123 //!< SCU.PMIC_I2C.SDA
+#define SC_P_PMIC_INT_B 124 //!< SCU.DSC.PMIC_INT_B
+#define SC_P_SCU_GPIO0_00 125 //!< SCU.GPIO0.IO00, SCU.UART0.RX, M40.UART0.RX, ADMA.UART4.RX
+#define SC_P_SCU_GPIO0_01 126 //!< SCU.GPIO0.IO01, SCU.UART0.TX, M40.UART0.TX, ADMA.UART4.TX
+#define SC_P_SCU_BOOT_MODE0 127 //!< SCU.DSC.BOOT_MODE0
+#define SC_P_SCU_BOOT_MODE1 128 //!< SCU.DSC.BOOT_MODE1
+#define SC_P_SCU_BOOT_MODE2 129 //!< SCU.DSC.BOOT_MODE2
+#define SC_P_SCU_BOOT_MODE3 130 //!< SCU.DSC.BOOT_MODE3
+#define SC_P_MIPI_DSI0_I2C0_SCL 131 //!< MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO4.IO00
+#define SC_P_MIPI_DSI0_I2C0_SDA 132 //!< MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO4.IO01
+#define SC_P_MIPI_DSI0_GPIO0_00 133 //!< MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO4.IO02
+#define SC_P_MIPI_DSI0_GPIO0_01 134 //!< MIPI_DSI0.GPIO0.IO01, LSIO.GPIO4.IO03
+#define SC_P_MIPI_DSI1_I2C0_SCL 135 //!< MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO4.IO04
+#define SC_P_MIPI_DSI1_I2C0_SDA 136 //!< MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO4.IO05
+#define SC_P_MIPI_DSI1_GPIO0_00 137 //!< MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO4.IO06
+#define SC_P_MIPI_DSI1_GPIO0_01 138 //!< MIPI_DSI1.GPIO0.IO01, LSIO.GPIO4.IO07
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 139 //!<
+#define SC_P_MIPI_CSI0_MCLK_OUT 140 //!< MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO4.IO08
+#define SC_P_MIPI_CSI0_I2C0_SCL 141 //!< MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO4.IO09
+#define SC_P_MIPI_CSI0_I2C0_SDA 142 //!< MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO4.IO10
+#define SC_P_MIPI_CSI0_GPIO0_00 143 //!< MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO4.IO11
+#define SC_P_MIPI_CSI0_GPIO0_01 144 //!< MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO4.IO12
+#define SC_P_QSPI0A_DATA0 145 //!< LSIO.QSPI0A.DATA0, MIPI_DSI0.I2C0.SCL
+#define SC_P_QSPI0A_DATA1 146 //!< LSIO.QSPI0A.DATA1, MIPI_DSI0.I2C0.SDA
+#define SC_P_QSPI0A_DATA2 147 //!< LSIO.QSPI0A.DATA2, MIPI_DSI1.I2C0.SCL
+#define SC_P_QSPI0A_DATA3 148 //!< LSIO.QSPI0A.DATA3, MIPI_DSI1.I2C0.SDA
+#define SC_P_QSPI0A_DQS 149 //!< LSIO.QSPI0A.DQS
+#define SC_P_QSPI0A_SS0_B 150 //!< LSIO.QSPI0A.SS0_B, MIPI_CSI0.I2C0.SCL
+#define SC_P_QSPI0A_SS1_B 151 //!< LSIO.QSPI0A.SS1_B, MIPI_CSI0.I2C0.SDA
+#define SC_P_QSPI0A_SCLK 152 //!< LSIO.QSPI0A.SCLK
+#define SC_P_QSPI0B_SCLK 153 //!< LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0
+#define SC_P_QSPI0B_DATA0 154 //!< LSIO.QSPI0B.DATA0, LSIO.QSPI1A.DATA0, LSIO.KPP0.COL1
+#define SC_P_QSPI0B_DATA1 155 //!< LSIO.QSPI0B.DATA1, LSIO.QSPI1A.DATA1, LSIO.KPP0.COL2
+#define SC_P_QSPI0B_DATA2 156 //!< LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3
+#define SC_P_QSPI0B_DATA3 157 //!< LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0
+#define SC_P_QSPI0B_DQS 158 //!< LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1
+#define SC_P_QSPI0B_SS0_B 159 //!< LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2
+#define SC_P_QSPI0B_SS1_B 160 //!< LSIO.QSPI0B.SS1_B, LSIO.QSPI1A.SS1_B, LSIO.KPP0.ROW3
+#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0 161 //!<
+#define SC_P_XTALI 162 //!< SCU.DSC.XTALI
+#define SC_P_XTALO 163 //!< SCU.DSC.XTALO
+#define SC_P_ANA_TEST_OUT_P 164 //!< SCU.DSC.TEST_OUT_P
+#define SC_P_ANA_TEST_OUT_N 165 //!< SCU.DSC.TEST_OUT_N
+#define SC_P_RTC_XTALI 166 //!< SNVS.RTC_XTALI
+#define SC_P_RTC_XTALO 167 //!< SNVS.RTC_XTALO
+#define SC_P_PMIC_ON_REQ 168 //!< SNVS.PMIC_ON_REQ
+#define SC_P_ON_OFF_BUTTON 169 //!< SNVS.ON_OFF_BUTTON
+/*@}*/
#endif /* _SC_PINS_H */
+
projects / linux.git / commitdiff