MLK-17232-3: dts: arm64: imx8mq: remove APB clock for rm67191 DTS

According to commit:

<8c9aa9e83e37> "MLK-16942-2: dts: Remove disp_apb clock rate setting"

APB clock is configured by ROM code and it should be 133MHz. Remove the
setting from this DTS.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts
index f4490d8..804a6c8 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts
@@ -27,20 +27,17 @@
        disp-dev = "mipi_disp";
 
        assigned-clocks = <&clk IMX8MQ_CLK_DISP_AXI_SRC>,
-                         <&clk IMX8MQ_CLK_DISP_APB_SRC>,
                          <&clk IMX8MQ_CLK_DISP_RTRM_SRC>,
                          <&clk IMX8MQ_CLK_DISP_RTRM_PRE_DIV>,
                          <&clk IMX8MQ_CLK_DC_PIXEL_SRC>,
                          <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
                          <&clk IMX8MQ_VIDEO_PLL1>;
        assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
-                                <&clk IMX8MQ_SYS2_PLL_125M>,
                                 <&clk IMX8MQ_SYS1_PLL_800M>,
                                 <&clk IMX8MQ_CLK_DISP_RTRM_CG>,
                                 <&clk IMX8MQ_VIDEO_PLL1_OUT>,
                                 <&clk IMX8MQ_CLK_25M>;
        assigned-clock-rates = <800000000>,
-                              <125000000>,
                               <400000000>,
                               <400000000>,
                               <120000000>,