MLK-16586-2 ARM64: dts: imx: enable multi-core rpmsg support

Because there are two m4 cores on imx8qm,
enable imx8qm multi-core rpmsg support

BuildInfo:
- SCFW a6fd9a48, IMX-MKIMAGE 0, ATF 0
- U-Boot 2017.03-imx_v2017.03_4.9.11_imx8_alpha+g258936c

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Robin Gong <yibin.gong@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Andy Duan <fugang.duan@nxp.com>
Tested-by: Andy Duan <fugang.duan@nxp.com>

diff --git a/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt b/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt
index 855a00b..d51250a 100644 (file)
--- a/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt
+++ b/Documentation/devicetree/bindings/rpmsg/imx-rpmsg.txt
@@ -3,9 +3,13 @@ i.MX RPMSG platform implementations
 Required properties:
 - compatible : "fsl,imx7d-rpmsg", "fsl,imx6sx-rpmsg".
   "fsl,rpmsg-bus", "simple-bus", "fsl,imx8qxp-rpmsg".
+  "fsl,imx8qm-rpmsg".
 - vdev-nums : The number of the remote virtual devices.
 - reg : The reserved DDR phisical memory used to store
   vring descriptors.
+- multi-core-id: The id number of the remote processors.
+  And it is optional for the legacy platforms, since they
+  only have one remote processors.
 
 
 =====================================================================
@@ -13,12 +17,15 @@ message unit module for RPMSG
 
 - mu_rpmsg : The message unit module used to do the communications
   between the asymmetric cores.
-- compatible : "fsl,imx8-mu", "fsl,imx6sx-mu"
+- compatible : "fsl,imx8-mu", "fsl,imx6sx-mu", "fsl,imx-mu-rpmsg1".
+  Different mu module would be used by the different remote processor.
+  The "fsl, imx6sx-mu" is used by the first remote processor.
+  The "fsl,imx-mu-rpmsg1" is used by the second remote process.
 - reg : Should contain MU registers location and length.
 - interrupts : interrupt mapping for RPMSG MU IRQ
 - interrupt-parent : A single value that points to the interrupt
   parent to which the child domain is being mapped.
-  Value must be "&intmux_cm40"
+  Value must be "&intmux_cm40" or "&intmux_cm41"
 
 Example:
 rpmsg: rpmsg{

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
index 493ef23..9339444 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2.dts
@@ -954,3 +954,17 @@
        reg = <0x0 0xb8000000 0x0 0x10000>;
        status = "okay";
 };
+
+&intmux_cm41 {
+       status = "okay";
+};
+
+&rpmsg1{
+       /*
+        * 64K for one rpmsg instance:
+        * --0xb8100000~0xb810ffff: pingpong
+        */
+       vdev-nums = <1>;
+       reg = <0x0 0xb8100000 0x0 0x10000>;
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
index 573edc9..6771055 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek.dts
@@ -424,3 +424,31 @@
        epdev_on-supply = <&epdev_on>;
        status = "okay";
 };
+
+&intmux_cm40 {
+       status = "okay";
+};
+
+&rpmsg{
+       /*
+        * 64K for one rpmsg instance:
+        * --0xb8000000~0xb800ffff: pingpong
+        */
+       vdev-nums = <1>;
+       reg = <0x0 0xb8000000 0x0 0x10000>;
+       status = "okay";
+};
+
+&intmux_cm41 {
+       status = "okay";
+};
+
+&rpmsg1{
+       /*
+        * 64K for one rpmsg instance:
+        * --0xb8100000~0xb810ffff: pingpong
+        */
+       vdev-nums = <1>;
+       reg = <0x0 0xb8100000 0x0 0x10000>;
+       status = "okay";
+};

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
index 963db57..ea8a04e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm.dtsi
@@ -985,6 +985,26 @@
                                power-domains =<&pd_cm40>;
                        };
                };
+
+               pd_cm41: PD_CM41 {
+                       compatible = "nxp,imx8-pd";
+                       reg = <SC_R_LAST>;
+                       #power-domain-cells = <0>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+
+                       pd_cm41_mu0a0: PD_CM41_MU0A0{
+                               reg = <SC_R_M4_1_MU_0A0>;
+                               #power-domain-cells = <0>;
+                               power-domains =<&pd_cm41>;
+                       };
+
+                       pd_cm41_intmux: PD_CM41_INTMUX {
+                               reg = <SC_R_M4_1_INTMUX>;
+                               #power-domain-cells = <0>;
+                               power-domains =<&pd_cm41>;
+                       };
+               };
        };
 
        tsens: thermal-sensor {
@@ -2913,6 +2933,26 @@
                status = "disabled";
        };
 
+       intmux_cm41: intmux@3b400000 {
+               compatible = "nxp,imx-intmux";
+               reg = <0x0 0x3b400000 0x0 0x1000>;
+               interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
+                               <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-controller;
+               interrupt-parent = <&gic>;
+               #interrupt-cells = <2>;
+               clocks = <&clk IMX8QM_CM41_IPG_CLK>;
+               clock-names = "ipg";
+               power-domains = <&pd_cm41_intmux>;
+               status = "disabled";
+       };
+
        imx_rpmsg: imx_rpmsg {
                compatible = "fsl,rpmsg-bus", "simple-bus";
                #address-cells = <2>;
@@ -2931,7 +2971,24 @@
                };
 
                rpmsg: rpmsg{
-                       compatible = "fsl,imx8qxp-rpmsg";
+                       compatible = "fsl,imx8qm-rpmsg";
+                       status = "disabled";
+               };
+
+               mu_rpmsg1: mu_rpmsg1@3b440000 {
+                       compatible = "fsl,imx8-mu", "fsl,imx-mu-rpmsg1";
+                       reg = <0x0 0x3b440000 0x0 0x10000>;
+                       interrupts = <31 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-parent = <&intmux_cm41>;
+                       clocks = <&clk IMX8QM_CM41_IPG_CLK>;
+                       clock-names = "ipg";
+                       power-domains = <&pd_cm41_mu0a0>;
+                       status = "okay";
+               };
+
+               rpmsg1: rpmsg1{
+                       compatible = "fsl,imx8qm-rpmsg";
+                       multi-core-id = <1>;
                        status = "disabled";
                };
        };