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(parent: 8465baa) | patch
clk: mediatek: update clock driver of MT2712
authorWeiyi Lu <weiyi.lu@mediatek.com>
Mon, 12 Mar 2018 07:03:42 +0000 (15:03 +0800)
committerStephen Boyd <sboyd@kernel.org>
Mon, 19 Mar 2018 21:37:40 +0000 (14:37 -0700)
commitf72595cf441bb534e601c609b687451cc9143f13
treeef0343f94f85124dcb877ed15ba7d12260bade0ftree | snapshot
parent8465baaecafc3d5c5b209a571ffbcc12983216f8commit | diff
clk: mediatek: update clock driver of MT2712

According to ECO design change,
1. add new clock mux data and change some
2. add new clock gate data and clock factor data
3. change status register offset of infra subsystem

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/mediatek/clk-mt2712.c diff | blob | history