projects / linux.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: d7fb34c) | patch
powerpc/tm: update comment about interrupt re-entrancy
authorNicholas Piggin <npiggin@gmail.com>
Fri, 28 Jun 2019 05:33:32 +0000 (15:33 +1000)
committerMichael Ellerman <mpe@ellerman.id.au>
Tue, 2 Jul 2019 11:39:49 +0000 (21:39 +1000)
commitf30a5e68f026f3214a9392391537adaa79996b24
treeaae2e59629903f03e463e905cf59b3c2eb510288tree | snapshot
parentd7fb34c704719d3c91455297678aa75d9da95817commit | diff
powerpc/tm: update comment about interrupt re-entrancy

Since the system reset interrupt began to use its own stack, and
machine check interrupts have done so for some time, r1 can be
changed without clearing MSR[RI], provided no other interrupts
(including SLB misses) are taken.

MSR[RI] does have to be cleared when using SCRATCH0, however.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/kernel/tm.S diff | blob | history