soc: fsl: dpio: change CENA regs to be cacheable

soc: fsl: dpio: change CENA regs to be cacheable

Change cache enabled regsiter accessed to be cacheable
plus non-shareable to meet the performance requirement.
QMan's CENA region contains registers and structures that
are 64byte in size and are inteneded to be accessed using a
single 64 byte bus transaction, therefore this portal
memory should be configured as cache-enabled. Also because
the write allocate stash transcations of QBMan should be
issued as cachable and non-coherent(non-sharable), we
need to configure this region to be non-shareable.

Signed-off-by: Haiying Wang <Haiying.Wang@nxp.com>