MIPS: only register FTLBPar exception handler for supported models
authorWANG Xuerui <git@xen0n.name>
Wed, 29 Jul 2020 13:14:15 +0000 (21:14 +0800)
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>
Fri, 31 Jul 2020 15:52:10 +0000 (17:52 +0200)
commitefd1b4ad3d5178a74387bc5ff69a2d4585f586c6
tree820e92edafd43538e37075f9a19c78a563302a16
parent48f5dd56cf2980ff932c6fd98ff5a2c503cde97b
MIPS: only register FTLBPar exception handler for supported models

Previously ExcCode 16 is unconditionally treated as the FTLB parity
exception (FTLBPar), but in fact its semantic is implementation-
dependent. Looking at various manuals it seems the FTLBPar exception is
only present on some recent MIPS Technologies cores, so only register
the handler on these.

Fixes: 75b5b5e0a262790f ("MIPS: Add support for FTLBs")
Reviewed-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: WANG Xuerui <git@xen0n.name>
Cc: Paul Burton <paulburton@kernel.org>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
arch/mips/include/asm/cpu-features.h
arch/mips/include/asm/cpu.h
arch/mips/kernel/cpu-probe.c
arch/mips/kernel/traps.c