riscv,entry: fix misaligned base for excp_vect_table
authorZihao Yu <yuzihao@ict.ac.cn>
Wed, 17 Mar 2021 08:17:25 +0000 (16:17 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 16 Apr 2021 09:43:21 +0000 (11:43 +0200)
commitefa7b6e4017aeccc0d7595e110f2d69a26332b2c
tree3721f6c4279619392470d46bfeb86168504e3fc9
parent6fbdce3cde97896ff4c2fb99e5d4bba45297a178
riscv,entry: fix misaligned base for excp_vect_table

[ Upstream commit ac8d0b901f0033b783156ab2dc1a0e73ec42409b ]

In RV64, the size of each entry in excp_vect_table is 8 bytes. If the
base of the table is not 8-byte aligned, loading an entry in the table
will raise a misaligned exception. Although such exception will be
handled by opensbi/bbl, this still causes performance degradation.

Signed-off-by: Zihao Yu <yuzihao@ict.ac.cn>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
arch/riscv/kernel/entry.S