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(parent: dcb899c) | patch
clk:aspeed: Fix reset bits for PCI/VGA and PECI
authorJae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Thu, 26 Apr 2018 17:22:32 +0000 (10:22 -0700)
committerStephen Boyd <sboyd@kernel.org>
Tue, 15 May 2018 22:02:23 +0000 (15:02 -0700)
commite76e56823a318ca580be4cfc5a6a9269bc70abea
treeba82caea099972bae97ddcd24867f14a76cfc933tree | snapshot
parentdcb899c47da9ff32e5156ddb9b2867f63ff7c4d0commit | diff
clk:aspeed: Fix reset bits for PCI/VGA and PECI

This commit fixes incorrect setting of reset bits for PCI/VGA and
PECI modules.

1. Reset bit for PCI/VGA is 8.
2. PECI reset bit is missing so added bit 10 as its reset bit.

Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Fixes: 15ed8ce5f84e ("clk: aspeed: Register gated clocks")
Cc: stable <stable@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/clk-aspeed.c diff | blob | history
include/dt-bindings/clock/aspeed-clock.h diff | blob | history