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MLK-14689 mx7ulp: Workaround APLL PFD2 to 345.6Mhz
authorYe Li <ye.li@nxp.com>
Thu, 13 Apr 2017 03:40:46 +0000 (11:40 +0800)
committerYe Li <ye.li@nxp.com>
Fri, 14 Apr 2017 03:11:19 +0000 (11:11 +0800)
commite72f766c98a3df9b620feb51484e33c7d50bed3c
tree2ff7ba7fee806e25393e91cc147e1081f14a88e6tree
parent636b19ace1205d82947eaa57958cd311e92edcf2commit | diff
MLK-14689 mx7ulp: Workaround APLL PFD2 to 345.6Mhz

The GPU uses APLL PFD2 as its clock parent (483.84Mhz) with divider set to 1.
This frequecy is out of ULP A0 spec. The MAX rate for GPU is 350Mhz.
So we simply configure the APLL PFD2 to 345.6Mhz (FRAC=28) to workaround the problem.
The correct fix should let GPU handle the clock rate in kernel.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit e931d534fd68e0e639082766de17a20e705fd908)
arch/arm/cpu/armv7/mx7ulp/clock.c diff | blob | history