MLK-19252-6 drm/bridge: sec-dsim: improve DPHY TIMING configs

MLK-19252-6 drm/bridge: sec-dsim: improve DPHY TIMING configs

The SEC provides a table to guide the DPHY TIMINGS config based
on the PLL output bit clock frequency for DSIM. So create the
table which is used by SEC LN14LPP DPHY with HS Timing v1.2 and
this table will be used by the SEC DSIM Bridge driver to help to
config the corresponding DPHY Timings correctly for each display
mode. Along with the table, a DPHY TIMING table entry 'compare'
method is implemented for the binary search when lookup the
suitable DPHY TIMING entry.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
(cherry picked from commit eb899b434be6127db26c370bf200d8072eaf01c4)
(cherry picked from commit 3b23233dafd65d6ea8c1fa12e8992c58ebc412bc)
(cherry picked from commit f83d7cac521cb4d20ac2f9093354f55055189ff7)