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(parent: 3dcbd36) | patch
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210
authorJoseph Lo <josephl@nvidia.com>
Wed, 29 May 2019 08:21:33 +0000 (16:21 +0800)
committerThierry Reding <treding@nvidia.com>
Tue, 12 May 2020 20:48:41 +0000 (22:48 +0200)
commitcd4d6f357545bc03112265b19e5ed50592812986
treec5c1e23047f2282d4b60353255a367d6b040964btree | snapshot
parent3dcbd36fa34ce9124ec51accd835130251f74213commit | diff
clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210

Introduce the low jitter path of PLLP and PLLMB which can be used as EMC
clock source.

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/clk/tegra/clk-tegra210.c diff | blob | history
include/dt-bindings/clock/tegra210-car.h diff | blob | history