MLK-15046 arm64: dts: fsl-imx8qxp: change CAN1 & 2 to use CAN0 clk and power domain

MLK-15046 arm64: dts: fsl-imx8qxp: change CAN1 & 2 to use CAN0 clk and power domain

Per information from Ranjani:
"Looks like all three CANs are controlled by one DSC clock slice
(SLSLICE[4]). Currently the SCFW is only allocating this clock to CAN0,
which explains why CAN0 works.  And once CAN0 is enabled, CAN1 and CAN2
access will also work."

This is a workaround patch to make CAN1 & CAN2 work temporarily.
Once SCFW supports shared clock management for all CAN, we can revert
this patch.

Cc: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Reviewed-by: Frank Li <frank.li@nxp.com>
Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>