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MLK-17689-3: arm64: dts: fsl-imx8mq-evk: Fix clocks for DCSS-RM67191
authorRobert Chiras <robert.chiras@nxp.com>
Thu, 8 Mar 2018 11:53:53 +0000 (13:53 +0200)
committerNitin Garg <nitin.garg@nxp.com>
Tue, 20 Mar 2018 19:56:24 +0000 (14:56 -0500)
commitca5b5ddd669a30ce5f06289531ac87e75b7ef1df
tree0caa426fee8de4716f79858c66df477d95f455c2tree
parent050bafd490c82680a6d4ae00e9923301c8dfcee8commit | diff
MLK-17689-3: arm64: dts: fsl-imx8mq-evk: Fix clocks for DCSS-RM67191

Currently, the default clock configuration for DCSS configures the pixel
clock to be sourced from VIDEO_PLL2, but this source cannot be used by the
DSI PHY_REF clock.
So, in order to make DCSS working with DSI, we need to have them both
(DCSS and DSI PHY) use the same clock source: VIDEO_PLL1.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-dcss-rm67191.dts diff | blob | history