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MLK-17022 drm/panel: panel-simple: Correct JDI TX26D202VM0BWA panel display timing...
authorLiu Ying <victor.liu@nxp.com>
Wed, 29 Nov 2017 06:10:16 +0000 (14:10 +0800)
committerNitin Garg <nitin.garg@nxp.com>
Tue, 20 Mar 2018 19:49:43 +0000 (14:49 -0500)
commitc7720e8e863c0678962f0309247d6d524a2144c8
tree403652cc4563cbe58a4ebe48f234dbdcacdc5987tree | snapshot
parentf82df90c2434334820123b418a10bd54ef5faf50commit | diff
MLK-17022 drm/panel: panel-simple: Correct JDI TX26D202VM0BWA panel display timing flags

The JDI TX26D202VM0BWA panel works in data enable(DE) mode.
Apparently, the panel's data enable signal is active high
according to the panel spec.  This patch corrects the DE
signal polarity from active low to active high.

Signed-off-by: Liu Ying <victor.liu@nxp.com>
drivers/gpu/drm/panel/panel-simple.c diff | blob | history