MLK-17189 imx8qxp: change the USDHC_CLK_ROOT source from AVPLL

MLK-17189 imx8qxp: change the USDHC_CLK_ROOT source from AVPLL

Currently, the DPLL of conn ss is not stable, will cause usdhc
data CRC error. So here change USDHC_CLK_ROOT source from AVPLL
as a workaround. And config USDHC1_CLK_ROOT to 333MHz, USDHC2_CLK_ROOT
to 200MHz. This workaround do not impact SD performance, but decrease
the eMMC performance, HS400ES work clock change from 198MHz to 166MHz,
read performance drop about 10%, write performance drop about 6%.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>