MLK-19961 drm/imx/dcss: Fix 27MHz pixel clock platform freeze

MLK-19961 drm/imx/dcss: Fix 27MHz pixel clock platform freeze

When the VIDEO_PLL2 clock code was moved to the DCSS driver, a
regression was introduced and any mode requiring a 27MHz pixel clock
would instantly freeze the platform.

It turns out, after setting the clocks in bypass mode, PLL_CLKE was
never set. Hence, DCSS was not getting any clock. Without a valid clock,
any attempt to access DTG registers will freeze the system.

This patch:
 * sets PLL_CLKE when bypass is used;
 * simplifies the pll code a little;
 * increases the atomic CRTC enable timeout to 500ms to accommodate the
   delay after which the clock is available when bypass is used;

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
CC: Oliver Brown <oliver.brown@nxp.com>