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(parent: f45f4f8) | patch
clk: uniphier: fix DAPLL2 clock rate of Pro5
authorMasahiro Yamada <yamada.masahiro@socionext.com>
Thu, 5 Oct 2017 02:32:59 +0000 (11:32 +0900)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 14 Dec 2017 08:28:24 +0000 (09:28 +0100)
commitc488c2e141bcce57a02d308df01d6f4172393637
tree8caf71a1672b9a078a8cf01eb98fb8ea81b4081btree | snapshot
parentf45f4f8a7cd89570b987ff101bcc510e9cfc2a9acommit | diff
clk: uniphier: fix DAPLL2 clock rate of Pro5

[ Upstream commit 67affb78a4e4feb837953e3434c8402a5c3b272f ]

The parent of DAPLL2 should be DAPLL1.  Fix the clock connection.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/clk/uniphier/clk-uniphier-sys.c diff | blob | history