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(parent: eee3258) | patch
drm/amd/display: Add Renoir registers (v3)
authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Thu, 25 Jul 2019 19:51:41 +0000 (15:51 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 29 Aug 2019 20:52:32 +0000 (15:52 -0500)
commitb593bce59bfa25d9abbf220b6614396ccd965b1b
tree94af24141159506509a8a446cd7b0f4a87d0189dtree | snapshot
parenteee3258e8f8be822a6d7c15faa3f4a9e3081381ecommit | diff
drm/amd/display: Add Renoir registers (v3)

add registers for dcn, clk, and renoir ip offsets

v2: header cleanup (Alex)
v3: Add DPCS registers (Hersen)

Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_offset.h [new file with mode: 0644] blob
drivers/gpu/drm/amd/include/asic_reg/clk/clk_10_0_2_sh_mask.h [new file with mode: 0644] blob
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_offset.h [new file with mode: 0644] blob
drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_2_1_0_sh_mask.h [new file with mode: 0644] blob
drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_offset.h [new file with mode: 0644] blob
drivers/gpu/drm/amd/include/asic_reg/dcn/dpcs_2_1_0_sh_mask.h [new file with mode: 0644] blob
drivers/gpu/drm/amd/include/renoir_ip_offset.h [new file with mode: 0644] blob