MLK-14693 mx7ulp: Change PLL rate calculation to avoid div 0

MLK-14693 mx7ulp: Change PLL rate calculation to avoid div 0

The new ROM patch will set DENOM and NUM of APLL and SPLL to 0 to
workaround PLL issue.
When DENOM is 0, the PLL rate calculation will divide 0 and raise a signal.

raise: Signal # 8 caught

To avoid such problem, we change our calculation.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit f28cf489e1b3864bac6bae4944d8a73bab30ec32)