MLK-20781-3 mx7ulp: clock: adjust LCDIF pixclock algorithm

MLK-20781-3 mx7ulp: clock: adjust LCDIF pixclock algorithm

Since LCDIF does not have a dedicated PLL as its source, we have to
find a best frequency closed to the target frequency. The previous
method is finding a closed clock with actual frequency higher than target.
But this causes problem to DSI PHY clock which uses target frequency to
calculate its clock parameters.  When the actaul pixclock is higher,
it may violates the requirement between DSI PHY clock and LCDIF pixclock clock.
clk_byte_freq >= dpi_pclk_freq * DPI_pixel_size / ( 8 * (cfg_num_lanes + 1))

So we'd better selecting a LCDIF clock not exceed the target frequency.

Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit fcd5fac9eb68c3bfed27c5a613315414f37b5990)
(cherry picked from commit ce59d991d21eaa929b20a50f168fde6d6bbfaaf4)