MLK-25282-1 arm64: dts: imx8mp: correct the pcie phy clock

MLK-25282-1 arm64: dts: imx8mp: correct the pcie phy clock

In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
OSC or internal system PLL. It is configured in the IOMUX_GPR14 register
directly, and can't be contolled by CCM at all.
So, correct it in the DTS node.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Jason Liu <jason.hui.liu@nxp.com>