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MLK-16986-1: phy: Fix Mixel PHY driver best_match
authorRobert Chiras <robert.chiras@nxp.com>
Tue, 5 Dec 2017 07:24:24 +0000 (09:24 +0200)
committerNitin Garg <nitin.garg@nxp.com>
Tue, 20 Mar 2018 19:50:22 +0000 (14:50 -0500)
commit7e95c9fefa2c49953e194580b8caef62e891f8ba
tree0471bf07df2863c910b63844a096a7ad3aab1a30tree | snapshot
parent804595685c224ed0fad8941138e1b1c03e814687commit | diff
MLK-16986-1: phy: Fix Mixel PHY driver best_match

When setting up the CM, CN and CO decimal values for DPHY PLL, these
values should only be rounded up when a "best_match" is requested. Some
DSI receivers requires the DSI clock to be exactly matched with the
pixel clock.

Signed-off-by: Robert Chiras <robert.chiras@nxp.com>
Reviewed-by: Laurentiu Palcu <laurentiu.palcu@nxp.com
drivers/phy/phy-mixel-mipi-dsi.c diff | blob | history