clk: sunxi-ng: A31: Fix spdif clock register
authorMarcus Cooper <codekipper@gmail.com>
Tue, 20 Dec 2016 10:44:46 +0000 (11:44 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Thu, 30 Nov 2017 08:39:11 +0000 (08:39 +0000)
commit7084a27375fa31ec66b620815949134cc35121db
tree8e7a13f72001529517e6dc272ec6a3c83dbda893
parentef5760f9600019dd13302263c1532706fe469c05
clk: sunxi-ng: A31: Fix spdif clock register

[ Upstream commit 70421257c068b91476e70cade15fca68045d0693 ]

As the SPDIF was rarely documented on the earlier Allwinner SoCs
it was assumed that it had a similar clock register to the one
described in the H3 User Manual.

However this is not the case and it looks to shares the same setup
as the I2S clock registers.

Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/clk/sunxi-ng/ccu-sun6i-a31.c