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(parent: 2bd6bf0) | patch
clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs
authorIcenowy Zheng <icenowy@aosc.io>
Sun, 10 Sep 2017 12:40:05 +0000 (20:40 +0800)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Sun, 17 Sep 2017 10:03:08 +0000 (12:03 +0200)
commit62d212bdb022deeb875f92f6e376c799e3f35eca
tree7ad60e3793d321145ba9c29de69f75523a42dba9tree | snapshot
parent2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66ecommit | diff
clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs

The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL
is really working.

Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when
trying to set PLL clock frequency without enabling it.

Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
drivers/clk/sunxi-ng/ccu-sun8i-h3.c diff | blob | history