clk: renesas: r8a7791/r8a7793: Fix LB clock divider
authorGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 29 Mar 2018 09:02:18 +0000 (11:02 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 16 Apr 2018 11:39:47 +0000 (13:39 +0200)
commit6041ce57f2c8c231017a1b4f7a71b606bb1c1016
treea4729eab64d6a0276f3a301c64e71bb3479abbc3
parent83fab8ea62ca74eaa51613ba8eeaf925f4f8087c
clk: renesas: r8a7791/r8a7793: Fix LB clock divider

The CLK_TYPE_GEN2_LB clock type is meant for SoCs like R-Car H2, where
the LB clock divider depends on the value of the MD18 pin.

On R-Car M2-W and M2-N, the LB clock divider is fixed to 24.  Hence
model the clock as a fixed factor clock instead.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
drivers/clk/renesas/r8a7791-cpg-mssr.c