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MLK-15949-2 ARM64: dts: fsl-imx8qxp: correct USDHC per clock rate
authorHaibo Chen <haibo.chen@nxp.com>
Tue, 11 Jul 2017 03:19:49 +0000 (11:19 +0800)
committerNitin Garg <nitin.garg@nxp.com>
Mon, 19 Mar 2018 20:33:34 +0000 (15:33 -0500)
commit5d50c6a3691051f3dfbb675b91d823a99eeb1cf6
tree14743fe2e124912a9427aa320fbcc6a26713e5adtree | snapshot
parent0efdbc636e31815e33ed336215e0bda9dbaa9849commit | diff
MLK-15949-2 ARM64: dts: fsl-imx8qxp: correct USDHC per clock rate

Set USDHC2/3 per clock's parent clock to 200MHz.

Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
arch/arm64/boot/dts/freescale/fsl-imx8qxp.dtsi diff | blob | history