MLK-21105 IPUv3: disp: Explicitly clear DI_GEN_POLARITY_DISP_CLK when necessary

MLK-21105 IPUv3: disp: Explicitly clear DI_GEN_POLARITY_DISP_CLK when necessary

The IPUv3 fb driver would call ipu_init_sync_panel() to enable a display.
It reads the DI_GENERAL register first and sets the bit
DI_GEN_POLARITY_DISP_CLK to high if sig.clk_pol is false.  This assumes
no one else would program the bit and the pixel clock polarity never
changes(which is usually the case).  However, the commit mentioned below
sets the bit to high in ipu_uninit_sync_panel() when a display is disabled,
in order to avoid power leakage for display pins.  This would keep the
bit being high as long as the display was disabled since the system is
actively running.  This patch explicitly clears the bit when necessary
to fix the issue.  Tests are done for CLAA-WVGA parallel LCD panel,
SEIKO-WVGA parallel LCD panel, Hannstar XGA LVDS panel(LVDS0 and LVDS1),
HIMAX WVGA MIPI DSI panel and native HDMI output on i.MX6q SabreSD board.

Fixes: 9afd177e7524 ("ENGR00141552 ipuv3: fix display pin's power leak")
Signed-off-by: Liu Ying <victor.liu@nxp.com>
(cherry picked from commit 02db8c7829d72bd45967d866965a17d818b9cc57)
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Shrikant Bobade <Shrikant_Bobade@mentor.com>
(cherry picked from commit 0f52c8a6d5c22f62e58109ae4ff8b1dad5c09348)