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MLK-17200-2 mx7ulp: Remove SNVS LP settings for B0
authorYe Li <ye.li@nxp.com>
Wed, 13 Dec 2017 06:20:15 +0000 (00:20 -0600)
committerYe Li <ye.li@nxp.com>
Wed, 13 Dec 2017 12:29:45 +0000 (06:29 -0600)
commit495d31773722a3ce2eb9c197eea9bbb1af619a61
tree1604a137600b1d4a0099758f1234b34f1574cbb1tree | snapshot
parent9ad30c8439ece3a8b88040847155405fca40facfcommit | diff
MLK-17200-2 mx7ulp: Remove SNVS LP settings for B0

Since i.MX7ULP B0 moves the SNVS LP into M4 domain, A core can't access
it. So check the CPU rev and not apply the settings for B0.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
arch/arm/cpu/armv7/mx7ulp/soc.c diff | blob | history
arch/arm/include/asm/arch-mx7ulp/imx-regs.h diff | blob | history