MLK-16689: Add DDR PHY training flow for different frequency

MLK-16689: Add DDR PHY training flow for different frequency

On our i.MX8MQ EVK board, we will support three frequency point:
    1. 3200mts, DDRC core clock is 800MHz;
    2. 400mts, DDRC core clock is 100MHz;
    3. 100mts, DDRC core clock is 25MHz.

The 1D training flow need to be run once for each frequency. The
PHY training updated to support training different frequency point.

Additionally, the DDRC's registers of other frequency also need to
be configured.

Signed-off-by: Bai Ping <ping.bai@nxp.com>