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MLK-23694-2 arm64: dts: imx8mp: assign 2079MHz to video_pll1
authorFancy Fang <chen.fang@nxp.com>
Mon, 16 Mar 2020 06:51:03 +0000 (14:51 +0800)
committerDong Aisheng <aisheng.dong@nxp.com>
Mon, 14 Dec 2020 03:22:40 +0000 (11:22 +0800)
commit42c81403882b8a62db9a64f835328c55afcbf1ea
treecc8c139ddc9b2e23f44bbed8dbdd3a2fa2237890tree
parent0a07c1b9c88e8f0f4eff58f9d0160787afa9675fcommit | diff
MLK-23694-2 arm64: dts: imx8mp: assign 2079MHz to video_pll1

The 'video_pll1' clock is shared by MIPI and LVDS displays
and each of the display has a specific requirement for the
PLL rate which can be satified by set 'video_pll1' rate to
be 2079MHz. So assign 2079MHz rate to 'video_pll1' under
CCM device.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Reviewed-by: Liu Ying <victor.liu@nxp.com>
arch/arm64/boot/dts/freescale/imx8mp.dtsi diff | blob | history