MLK-11759 mxc IPUv3: common: Config IPU_CONF correctly in ipu_enable_channel()

MLK-11759 mxc IPUv3: common: Config IPU_CONF correctly in ipu_enable_channel()

The register IPU_CONF contains several dedicated enable bits for IPU internal
modules.  When we enable an IPU logic channel, e.g., MEM_BG_SYNC, by calling
the function ipu_enable_channel(), we should enable the necessary IPU internal
modules for that logic channel instead of touching other irrelevant modules.
This may most definitely keep the steps for enabling a logic channel steady
if no IPU internal module is shared by different logic channels.

An known issue is caused by breaking this rule: we are likely to switch the
display pixel clock source from IPU internal HSP clock to external clock when
enabling a display which is driven by MEM_BG_SYNC.  This operation is safe if
the relevant DI enable bit in IPU_CONF is zero.  In case another task, e.g.,
MEM_PP_MEM, is being enabled in parallel, it may accidently set the DI enable
bit to one before the pixel clock source is switched, which may cause the
display engine malfunction.  To fix this issue, this patch configures the
register IPU_CONF correctly in the function ipu_enable_channel() according to
specific IPU logic channels.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>