MLK-17200-3 mx7ulp: Select the SCG1 APLL PFD as a system clock source
authorYe Li <ye.li@nxp.com>
Wed, 13 Dec 2017 06:22:09 +0000 (00:22 -0600)
committerYe Li <ye.li@nxp.com>
Fri, 24 May 2019 11:28:41 +0000 (04:28 -0700)
commit3b3de39cf1f20107e39ed20746c82d3bc737d532
tree871e1e11bec7514e901a17b80840904a10e9c269
parent56e307949c17169fbd98ac70843e6bd859e07602
MLK-17200-3 mx7ulp: Select the SCG1 APLL PFD as a system clock source

Due to the APLL out glitch issue TKT332232, the APLLCFG PLLS bit must be set
to select SCG1 APLL PFD for generating system clock to align with the design.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 242823400c5bd59960e1b40d941e177e8ebad57e)
(cherry picked from commit 3c8d8b0a95f8b1132e301e7e00955846b12aa4cc)
board/freescale/mx7ulp_evk/imximage.cfg
board/freescale/mx7ulp_evk/plugin.S