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(parent: df96401) | patch
clk: qcom: ipq8074: fix missing GPLL0 divider width
authorAbhishek Sahu <absahu@codeaurora.org>
Wed, 13 Dec 2017 14:25:34 +0000 (19:55 +0530)
committerStephen Boyd <sboyd@codeaurora.org>
Fri, 22 Dec 2017 00:03:26 +0000 (16:03 -0800)
commit32cae024f7186e60cbdeb5b594eb920036f38225
tree60c329621e6f73ada01bf8288db2232bb0810d01tree | snapshot
parentdf964016490b2cf630b1b926a1d5c610833aaa84commit | diff
clk: qcom: ipq8074: fix missing GPLL0 divider width

GPLL0 uses 4 bits post divider which should be specified
in clock driver structure.

Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
drivers/clk/qcom/gcc-ipq8074.c diff | blob | history