MLK-17239 mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue
authorHaibo Chen <haibo.chen@nxp.com>
Tue, 19 Dec 2017 06:46:55 +0000 (14:46 +0800)
committerHaibo Chen <haibo.chen@nxp.com>
Tue, 19 Dec 2017 08:28:40 +0000 (16:28 +0800)
commit2f1eed596782be19eb2c14e708e6db8596876346
tree9a853d35d68419be602b9560422db63b9fd21a42
parent3bc93fa619c29b1344002ef4d96478bf8f9a2fde
MLK-17239 mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue

When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
the actual clock rate is just half of the expected clock.

This patch set the DDR_EN bit first for DDR mode, hardware divide
the usdhc clock automatically, then follow the original sdr clock
setting method.

This patch also remove the unused variable 'is_ddr'.

Acked-by: Li Ye <ye.li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
drivers/mmc/fsl_esdhc.c