MLK-17586-3 i.MX7ULP: change USDHC clock rate

MLK-17586-3 i.MX7ULP: change USDHC clock rate

Change USDHC0 and USDHC1 per clock source from APLL_PFD1,
and set the APll_PFD1 clock rate to 352.8MHz.

Also gate off APll_PFD1/2/3 before boot OS, otherwise set
the clock rate of APll_PFD1/2/3 during OS boot up will triger
some warning message.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
(cherry picked from commit 07ef0fab23204684d82f27baf721a72b247f30c5)
(cherry picked from commit 1c30a73542990afbe48bf7a398baba9c5efaf4fe)
(cherry picked from commit 0e4ce4b6b3f8d06f5b63850e04a1e4deb9b07624)
(cherry picked from commit 113a509e4d4ea84b55b296efa5f760b7192f9487)
(cherry picked from commit e01af8fc7daf0700c13f46e985e2e956f753feff)