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(parent: e6cfa64) | patch
clk: ingenic: support PLLs with no bypass bit
authorPaul Cercueil <paul@crapouillou.net>
Tue, 16 Jan 2018 15:47:53 +0000 (16:47 +0100)
committerJames Hogan <jhogan@kernel.org>
Thu, 18 Jan 2018 22:05:13 +0000 (22:05 +0000)
commit268db077ac47d3b5d8e3a768bf9dc5cb32ce6074
tree59380382f525ff4869a1ac1d5b586fde3059ea48tree | snapshot
parente6cfa64375d34a6c8c1861868a381013b2d3b921commit | diff
clk: ingenic: support PLLs with no bypass bit

The second PLL of the JZ4770 does not have a bypass bit.
This commit makes it possible to support it with the current common CGU
code.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Maarten ter Huurne <maarten@treewalker.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/18479/
Signed-off-by: James Hogan <jhogan@kernel.org>
drivers/clk/ingenic/cgu.c diff | blob | history
drivers/clk/ingenic/cgu.h diff | blob | history