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(parent: 495d317) | patch
MLK-17200-3 mx7ulp: Select the SCG1 APLL PFD as a system clock source
authorYe Li <ye.li@nxp.com>
Wed, 13 Dec 2017 06:22:09 +0000 (00:22 -0600)
committerYe Li <ye.li@nxp.com>
Wed, 13 Dec 2017 12:29:45 +0000 (06:29 -0600)
commit242823400c5bd59960e1b40d941e177e8ebad57e
treef43bae9f1296e129390870b76fb3b14e9ef24b95tree | snapshot
parent495d31773722a3ce2eb9c197eea9bbb1af619a61commit | diff
MLK-17200-3 mx7ulp: Select the SCG1 APLL PFD as a system clock source

Due to the APLL out glitch issue TKT332232, the APLLCFG PLLS bit must be set
to select SCG1 APLL PFD for generating system clock to align with the design.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
board/freescale/mx7ulp_evk/imximage.cfg diff | blob | history