MLK-20049-2 imx8mm_val: Add DDR3L validation board support
authorYe Li <ye.li@nxp.com>
Wed, 26 Sep 2018 03:27:48 +0000 (20:27 -0700)
committerYe Li <ye.li@nxp.com>
Fri, 24 May 2019 09:33:59 +0000 (02:33 -0700)
commit1d2b21957c29de5691103fb25e0f340e17ac1c06
tree36f1365e4caaf72a3f4a985cfcd240549c7b23f7
parent2257fe832100960b1cac96b92ecdd21d581bf33b
MLK-20049-2 imx8mm_val: Add DDR3L validation board support

Add DDR3 init codes, board codes, defconfig and DTS into u-boot.
Basic modules are ready: SD, UART, I2C, USB host and NAND.

There is a FPGA on this board. It controls WDOG_B, and ENET PHY RESET.
So reset and ethernet won't work at default.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 1742883a1e9c6a02045f81a14e4aa833c781afe9)
17 files changed:
arch/arm/dts/Makefile
arch/arm/dts/fsl-imx8mm-ddr3l-val.dts [new file with mode: 0644]
arch/arm/mach-imx/imx8m/Kconfig
board/freescale/imx8mm_val/Kconfig
board/freescale/imx8mm_val/ddr/Makefile
board/freescale/imx8mm_val/ddr/ddr3l/Makefile [new file with mode: 0644]
board/freescale/imx8mm_val/ddr/ddr3l/anamix_common.h [new file with mode: 0644]
board/freescale/imx8mm_val/ddr/ddr3l/ddr3_define.h [new file with mode: 0644]
board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_task.c [new file with mode: 0644]
board/freescale/imx8mm_val/ddr/ddr3l/ddr3_phyinit_train_sw_ffc_fw09.c [new file with mode: 0644]
board/freescale/imx8mm_val/ddr/ddr3l/ddr3_sw_fast_freq_chg_fw09.c [new file with mode: 0644]
board/freescale/imx8mm_val/ddr/ddr3l/restore_1d2d_trained_csr_ddr3_p012.c [new file with mode: 0644]
board/freescale/imx8mm_val/ddr/ddr3l/save_1d2d_trained_csr_ddr3_p012.c [new file with mode: 0644]
board/freescale/imx8mm_val/imx8mm_val.c
board/freescale/imx8mm_val/spl.c
configs/imx8mm_ddr3l_val_defconfig [new file with mode: 0644]
include/configs/imx8mm_val.h