MLK-17439 mx7ulp: Change clock rate calculation for NIC1 BUS and EXT
authorYe Li <ye.li@nxp.com>
Mon, 22 Jan 2018 03:22:40 +0000 (19:22 -0800)
committerYe Li <ye.li@nxp.com>
Mon, 22 Jan 2018 05:12:06 +0000 (21:12 -0800)
commit1a53e025c6be73a84570a3857cb709d98e49ef96
treea4cf94a5a81a8a6c9122aa417499dbeabd5721ab
parent9ce009caf4c80fbcb31526049420d6c388494247
MLK-17439 mx7ulp: Change clock rate calculation for NIC1 BUS and EXT

On i.MX7ULP B0, there is change in NIC clock dividers architecture.
On A0, the NIC1 BUS and EXT dividers were in a chain with NIC1 DIV, but
on B0 they are parallel with NIC1 DIV. So now the dividers are independent.
This patch modifies the scg_nic_get_rate function according to this change.

Signed-off-by: Ye Li <ye.li@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
arch/arm/cpu/armv7/mx7ulp/scg.c