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(parent: a286039) | patch
MLK-17586-3 i.MX7ULP: change USDHC clock rate
authorHaibo Chen <haibo.chen@nxp.com>
Wed, 14 Mar 2018 09:15:23 +0000 (17:15 +0800)
committerHaibo Chen <haibo.chen@nxp.com>
Mon, 26 Mar 2018 09:40:44 +0000 (17:40 +0800)
commit07ef0fab23204684d82f27baf721a72b247f30c5
treeef5cff7bbb8c7f6be31ae6f3eefd6e81d08a567dtree | snapshot
parenta28603934e6ba2f07b92714b462df1e5e494bce6commit | diff
MLK-17586-3 i.MX7ULP: change USDHC clock rate

Change USDHC0 and USDHC1 per clock source from APLL_PFD1,
and set the APll_PFD1 clock rate to 352.8MHz.

Also gate off APll_PFD1/2/3 before boot OS, otherwise set
the clock rate of APll_PFD1/2/3 during OS boot up will triger
some warning message.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
arch/arm/cpu/armv7/mx7ulp/clock.c diff | blob | history
arch/arm/cpu/armv7/mx7ulp/scg.c diff | blob | history
arch/arm/cpu/armv7/mx7ulp/soc.c diff | blob | history
arch/arm/include/asm/arch-mx7ulp/scg.h diff | blob | history